1. Field of the Invention
The present invention relates to an output buffer in a semiconductor integrated circuit device, and more particularly to an output buffer in which resistance against electrostatic breakdown is enhanced or improved.
2. Description of the Related Art
A conventional output buffer of the kind to which the present invention relates is shown in FIG. 1A. The conventional output buffer has a series circuit connected between a power supply terminal V.sub.CC and a ground terminal V.sub.SS, which is formed by an n-channel MOS field effect transistor (hereinafter referred to as "MOSFET") M11 receiving at its gate a first output data control signal D11 and an n-channel MOSFET 712 receiving at its gate a second output data control signal D12. A common junction node X1 defined between these two n-channel MOSFETs M11 and M12 is connected to a bonding pad PAD which is connected with an output terminal of the semiconductor integrated circuit device.
Next, the operation of the above described output buffer will be explained.
When the first output data control signal D11 is at a high level and the second output data control signal D12 is at a low level, the n-channel MOSFET M11 turns to a conductive state and the n-channel MOSFET M12 turns to a non-conductive state, so that the data outputted by the n-channel MOSFET M11 becomes a high level. On the contrary, when the first output data control signal D11 is at a low level and the second output data control signal D12 is at a high level, the n-channel MOSFET M11 turns to its non-conductive state and the n-channel MOSFET M12 turns to its conductive state, so that the data outputted by the n-channel MOSFET M12 becomes a low level.
However, in semiconductor integrated circuit devices for which minitualization is being advanced, to prevent degradation by the hot carrier in the element, the devices are being formed with a lightly doped drain (LDD) structure. In other words, in this type of MOSFETs, as shown in FIG. 2, a gate electrode 203 is formed on a p-type semiconductor substrate 201 with a gate silicon dioxide layer 202 being disposed therebetween, and there are formed at both sides of the gate electrode 203 a drain region constituted by an n.sup.+ -diffusion layer 204 and an n.sup.- -diffusion layer 205, and a source region constituted by an n.sup.+ -diffusion layer 206 and an n.sup.- -diffusion layer 207.
The above mentioned conventional output buffer had a disadvantage in that, because it was made with the LDD structure MOSFETs, its resistance against electrostatic breakdown was insufficient.
In an LDD structure MOSFET as shown in FIG. 2, if a high voltage is applied to the drain thereof, avalanche breakdown occurs in the vicinity of the gate electrode of the drain electrode, that is, at the n.sup.- -diffusion layer 205, and holes are injected into the p-type semiconductor substrate 201. As a result, the potential of the semiconductor substrate 201 rises, the region between the source region (n.sup.+ -diffusion layer 206 and n.sup.- -diffusion layer 207) and the semiconductor substrate 201 becomes biased in the forward direction, and electrons are injected into the substrate 201 from the source region. As a result, the MOSFET operates in a state near negative-resistance and excessive current flows in the n.sup.- -diffusion layer 205 forming the drain region, and this drain region is destroyed by heat due to the high resistance value of this diffusion layer.
To cope with this, as shown in FIG. 1B, there is a method in which a resistor element R is connected between the junction node X1 of the MOSFETs M11, M12 and the bonding PAD to enhance the resistance against electrostatic breakdown, but to attain the required resistance against the electrostatic breakdown, a resistor having a high resistance value must be used, and in this case, the current drivability of the output buffer is reduced, and the lowering of the operation speed becomes a problem.